Split-Gate flash memory cell arrays are well known in the art. One example of such an array is disclosed in U.S. Pat. No. 7,927,994, which is incorporated herein by reference for all purposes. FIG. 1 illustrates the known memory cell structure. Specifically, the memory cells each have four gates: a floating gate 10 (disposed over and controlling the conductivity of a first portion of a channel region 12 that extends between the source region 14 and the drain region 16), a control gate 18 (disposed over the floating gate 10), an erase gate 20 (disposed over the source region 14, and shared between two adjacent memory cells), and a select gate 22 (also referred to as word line WL, disposed over and controlling the conductivity of a second portion of the channel region 12).
Capacitive coupling between the control gate 18 and the floating gate 10 during operation is achieved by forming the control gate 18 over the floating gate 10 (preferably in a self-aligned manner) with an ONO insulator (oxide/nitride/oxide) or other dielectric(s) between them as an Inter-Poly-Dielectric (IPD). Capacitive coupling is dictated by the thickness of the intermediary dielectric(s), and the relative surface areas of the two gates that are positioned adjacent each other.
With advanced technology nodes whereby the size of the substrate surface allotted to each memory cell is reduced, the critical dimension (in the lateral direction) of the control gate is shrunk, which results in a reduction in the capacitive coupling between the floating gate 10 and control gate 18 (due to the reduced surface area sizes of the two gates adjacent to each other). Additionally, the tunnel oxide between the floating gate 10 and the erase gate 20 (through which electrons tunnel during an erase operation) is exposed to subsequent logic oxide nitridation or HKMG (high-K metal gate) processing. Therefore, the quality of the tunnel oxide is difficult to control. These two issues make it difficult to scale down the sizes of these types of memory cells.